Math Co-processor 1. Title: Math Coprocessor Prepared By: Tabeen Tasneem Tazeen Tasneem Department of Computer Science. Features: It is a high performance numeric co-processor. It can work on integer, decimal and real type numbers. It has an instruction set capable. Not all of the original co-processors were for floating point math. Intel itself offered an I/O coprocessor for the and called the


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The two came up with a revolutionary design with 64 bits of mantissa and 8087 math coprocessor bits of exponent for the longest format real number, with a stack architecture CPU and 8 bit stack registers, with a computationally rich instruction set.

The design solved a few outstanding known problems in numerical computing and numerical software: Palmer credited William Kahan 's writings on floating point as a significant influence on their design. Eventually, the design was 8087 math coprocessor to Intel Israel, and Rafi Nave was assigned to lead the implementation of the chip.


8087 math coprocessor Palmer, 8087 math coprocessor and Nave were awarded patents for the design. It worked in tandem with the or and introduced about 60 new instructions. The binary encodings for all instructions begin with the bit patterndecimal 27, the same as the ASCII character ESC although in the higher order bits of a byte; similar instruction prefixes are also sometimes referred to as " escape codes ".

The instruction mnemonic assigned by Intel for these coprocessor instructions is "ESC".


For an instruction with a memory operand, if the instruction called for the operand to be read, the would take the word of data read by the main CPU from 8087 math coprocessor data bus.

If the operand to be read was longer than one word, 8087 math coprocessor would also copy the address from the address bus; then, after completion of the data read cycle driven by the CPU, the would immediately use DMA to take control of the bus and transfer the additional bytes of the operand itself.

Intel - Were there coprocessors other than the ? - Retrocomputing Stack Exchange

If an instruction with a memory operand called for that operand to be written, the would ignore the read word on the data bus 8087 math coprocessor just copy the address, then request DMA and write the entire operand, in the same way that it would read the end of an extended operand.

As a consequence of this design, the could only operate on operands taken either from memory or from its own registers, and any exchange of data between the and the or was only via RAM. The main CPU program continued to execute while the executed an instruction; from the perspective of the main or CPU, a coprocessor instruction took only as long as the processing of the opcode and any memory operand cycle 2 clock cycles for no operand, 8 clock cycles plus the EA calculation time [5 to 12 clock cycles] for a memory operand [plus 4 more clock cycles on an ], to transfer the second 8087 math coprocessor of the operand wordafter which the CPU would begin executing the next instruction of the program.

Thus, a system with an was capable 8087 math coprocessor true parallel processing, performing one operation in the integer ALU of the main CPU while at the same time performing a floating-point operation in the coprocessor.


It is not necessary to use a WAIT instruction before an operation if the program uses other means to ensure that enough time elapses between the issuance of timing-sensitive instructions so that the can never receive such 8087 math coprocessor instruction before it completes the previous one.

It is also not necessary, if a WAIT is used, that it immediately precede the next instruction. Because the instruction prefetch queues of the and make the time when an instruction is executed not always the same as the time it is fetched, a coprocessor such as the cannot determine when an instruction for itself is the next instruction to be executed purely by watching the CPU bus.

The and 8087 math coprocessor two queue status signals which are connected to the coprocessor to allow it to synchronize with the CPU's internal timing of execution of instructions from its prefetch queue.

Intel 8087

The maintains its own identical prefetch queue, from which it reads the coprocessor opcodes that it actually executes. Hauppage made 8087 math coprocessor line of mother boards they referred to as These had a separate i The 'Cray 1 on a chip' that ran in parallel to the In addition to all of this, there were also the expected x87 clones with 8087 math coprocessor features.

These would run at higher IPC than the Intel originals and some of them offered additional instructions. I don't remember the details, but I think the IIT chips had specific instructions targeted at 4x4 matrices.

On original Intel chips, there were a few other interesting combinations. In response to the lag between the and the 's availability, early machines could be equipped with an The flip side of that was the XL, which was an chip that could be installed into an machine.

For a while, there were also ways to take advantage of the split bus and computational units of the I remember devices that would use this to let you run the core of your faster than the bus speed of the Not to mention all the rigamarole people would go to to overclock the main CPU itself.

The original PC AT shipped at 6MHz, although enterprising owners would install alternative crystals to run the machine at faster clocks.

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